7400 Contest Entry: i2s DAC with class D output

This is my entry for the 7400 Logic Competition. A little bit last minute, and hopefully I can get everything finished before the cutoff tonight.

I’m using a SN74HC132 hex NAND gate, a CD4094BE 8 bit shift register, two CD4585BE 4 bit comparators, a SN74HC590 8 bit counter, and a SN74HCU04 hex inverter.

The basic operation is as follows:

A 3MHz master clock signal is input from the i2s master into the 74590 counter which when divided by 256 is equal to 11,718kHz which I used for my word clock(wclk). This is also going to be the sample rate of my audio signal. I then use the wclk as a gate (utilizing the 74132 NAND chip) for the data clock (clk) to the shift register as well as to clear the counter. After the data is shifted into the 4094 shift register it is then compared against the counter which is continuously incrementing from 0 to 255. The output of the comparator is then fed into a 7404 inverter to buffer the output which drives an N-channel and P-channel MOSFET creating a half-H bridge and driving the speaker through an LC lowpass filter.

This ended up being more of a proof of concept as I ran out of time to debug everything. There are some bugs that need to be worked out, but I didn’t have any logic analyzer to debug the 8 bit bus. However, the frequency sweep shows everything working for the most part!
Thank you for taking a look!
The demo code I used on the LPC1769 is available on my GitHub repository.